The invention has specific, though by no means exclusive, application to digital circuits with built-in self-testing mechanisms, particularly those configured in modular form and appropriate, for example, for use in microprocessor-based systems employing buses for data and address transfer.
Such digital circuits may be functional modules such as read-only memories (ROM's), random access memories (RAM's), arithmetic logic units (ALU's), or input/output (I/O) devices. Clocked latches would normally be used to interface such modules with data buses for data transfer. For purposes of self-testing, the latches might be replaced with built-in logic block observers (BILBO's), one such BILBO being associated with the input terminals of the modules principal circuit, and the other, with the output terminals. The BILBO's function not only as conventional data latches for purposes of normal module operation, but have modes of operation in which one BILBO serves as a pseudorandom data generator, applying various digital test patterns to the input terminals of the principal circuit associated with the module, and in which the other BILBO serves as a signature analyzer which compresses the output data produced by the circuit under test into a unique set of data bits or signature. The resulting signature can be compared with a predetermined expected signature to determine whether the circuit under test is function properly.
BILBO's have typically been shift registers with feedback logic gates coupling the output terminals of higher order flip-flops to a multiplexor associated with the input terminal of the lowest order flip-flop. With appropriate signal gating circuitry, and upon application of appropriate control signals to such circuitry, as, for example, to disable the feedback gates, the shift register can function in four distinct modes: as a conventional data latch; as a conventional linear shift register; as a pseudorandom data generator; and as a signature analyzer. As a pseudorandom data generator, the contents of the shift register runs through a pseudorandom sequence with a predetermined maximum period dependent on the number of flip-flops involved and the characteristic polynomial created by the associated feedback gates.
A principal problem associated with using linear feedback shift registers in such applications relates to the need to tap the output terminals of selected flip-flops in the shift register and to feed their state values through appropriate logic gates to a multiplexor associated with the lowest order bit. An immediate concern is selecting appropriate feedback taps is that their configuration is not independent of the length of the register for maximum length polynominal division. Another potential problem relates to finding an appropriate circuit topology which can accommodate the required feedback from higher order flip-flops to the input multiplexor, particularly as the shift register is made large.